[Architecture] SuperH 32-bit RISC series (SH-4, ST40 system architecture)
by eoseontaek 2010. 8. 4. 12:09
[device] DDR2SDRAM : EDE1108ACBG
2010.09.06
HDCP Specification
2010.08.24
[Device] SDRAM latency
2010.08.03
[Glossary] tri-state
2010.07.21