2010. 8. 4. 12:09
SH-4 CPU Core Architecture
SH-4, ST40 system architecture, volume 1 : system
SH-4, ST40 system architecture, volume 2 : bus interfaces
STMicroelectronics
http://www.st.com/stonline/stappl/productcatalog/app?path=/pages/stcom/PcStComDocumentTableView.showTechlitTreeDocs&level0=141&level1=1735&level2=676&level3=0&doctype=7&doctypecode=um&enttype=4&tname=TL_USER_MANUAL_TREE_X_DOC&latest=N
'[C-05] STi7105' 카테고리의 다른 글
[device] DDR2SDRAM : EDE1108ACBG (0) | 2010.09.06 |
---|---|
HDCP Specification (0) | 2010.08.24 |
[Device] SDRAM latency (0) | 2010.08.03 |
[Glossary] tri-state (0) | 2010.07.21 |
DVB-S2 (0) | 2010.04.19 |